An example of multi-stage amplifiers are low-dropout (LDO) regulators which are linear voltage regulators which can operate with small input-output differential voltages. A typical LDO regulator 100 is illustrated in FIG. 1a. The LDO regulator 100 comprises an output amplification stage 103, e.g. a field-effect transistor (FET), at the output and a differential amplification stage or differential amplifier 101 (also referred to as error amplifier) at the input. A first input (fb) 107 of the differential amplifier 101 receives a fraction of the output voltage Vout determined by the voltage divider 104 comprising resistors R0 and R1. The second input (ref) to the differential amplifier 101 may be a stable voltage reference Vref 108 (also referred to as the bandgap reference). If the output voltage Vout changes relative to the reference voltage Vref, the drive voltage to the output amplification stage, e.g. the power FET, changes by a feedback mechanism called main feedback loop to maintain a constant output voltage Vout.
The LDO regulator 100 of FIG. 1a further comprises an additional intermediate amplification stage 102 configured to amplify the output voltage of the differential amplification stage 101. As such, an intermediate amplification stage 102 may be used to provide an additional gain within the amplification path. Furthermore, the intermediate amplification stage 102 may provide a phase inversion.
In addition, the LDO regulator 100 may comprise an output capacitance Cout (also referred to as output capacitor or stabilization capacitor or bybass capacitor) 105 parallel to the load 106. The output capacitor 105 is used to stabilize the output voltage Vout subject to a change of the load 106, in particular subject to a change of the load current Iload. It should be noted that typically the output current Iout at the output of the output amplification stage 103 corresponds to the load current Iload through the load 106 of the regulator 100 (apart from typically minor currents through the voltage divider 104 and the output capacitance 105). Consequently, the terms output current Iout and load current Iload are used synonymously, if not specified otherwise.
Typically, it is desirable to provide a stable output voltage Vout, even subject to transients of the load 106. By way of example, the regulator 100 may be used to provide a stable output voltage Vout to the processor of an electronic device (such as a smartphone). The load current Iload may vary significantly between a sleep state and an active state of the processor, thereby varying the load 106 of the regulator 100. In order to ensure a reliable operation of the processor, the output voltage Vout should remain stable, even in response to such load transients.
At the same time, the LDO regulator 100 should be able to react rapidly to load transients, i.e. the LDO regulator 100 should be able to rapidly provide the requested load current Iload, subject to a load transient. This means that the LDO regulator 100 should exhibit a high bandwidth.
Usually the settling time of the output voltage Vout, subject to a load transient, is dependent on the starting load current from which a load increases up to e.g. a maximum load. Load transient responses may be distinguished between the case where the load current increases from 0 mA to the maximum load current Imax and the case where the load current increases from e.g. 1 mA to Imax. These load transient responses may be substantially different from one another. As will be outlined in the present document, this is mainly due to a substantial mirror ratio of the output stage 103 and due to a large range of output currents. Since a relatively high ratio is typically important for low current applications, the performance and stability may be defined and/or limited by this mirror ratio. In order to improve the performance and stability, nonlinear current mirrors may be used. However, it has been observed that even when using nonlinear current mirrors, the settling speed of the output voltage Vout is still limited. As will be outlined in the present document, the limitation of the settling speed is mainly due to a relatively large load capacitance which is formed by the pass device of the output stage 103.
The present document is directed at providing amplifiers which provide an improved trade-off between stability and bandwidth (or response speed), subject to load transients. In particular, the present document addresses the technical problem of providing an output stage 103 of an amplifier 100 having a reduced settling time and an improved stability, subject to a load transient.